ELEC2
Further Electronics
Revision Notes
• In series:-
• In parallel:-
Contents
• Time Constant.
- Time to charge to 0.63Vs
- Time to discharge to 0.37Vs
• Time to charge to 0.5Vs=0.69RC
• Time to fully charge or discharge
= 5RC
Contents
T = 1.1 × R × C
- TRIGGER input goes below 1/3Vs,
- OUTPUT goes high and
DISCHARGE switches off,
- C charges through R,
- Until capacitor voltage =2/3Vs (THRESHOLD)
- OUTPUT goes low and
DISCHARGE switches on
- Capacitor discharged.
Contents
tH = 0.7(R1 + R2)C
tL = 0.7R2C
T = 0.7(R1 + 2R2)C
- When first switched on, TRIGGER is less than 1/3Vs,
- OUTPUT goes high, DISCHARGE switches off,
- Capacitor charges through R1 and R2,
- Until capacitor voltage = 2/3Vs (THRESHOLD),
- OUTPUT goes low, DISCHARGE switches on,
- Capacitor discharges through R2,
- Until capacitor voltage = 1/3Vs (TRIGGER),
- OUTPUT goes high, process repeats.
Contents
• When the
SET input is briefly taken to logic 0, the
Q output will become logic 1 and the
output will become logic 0.
• When the
RESET input is now briefly taken to logic 0,
Q will become logic 0 and the
output will become logic 1.
- S sets Q to 1
- R resets Q to 0
- Independent of the state of CK.
- On the rising edge of CK, Q is set to the logic state of D.
Contents
- Enables data to be outputted from data bus.
- Processor sets valid data onto data bus and then pulses CK high.
- Data captured and stored in latches.
- One flip-flop needed per bit.
Contents
• On the rising edge of each clock pulse, the data from a D-type flip-flop is stored in the next D-type flip-flop.
• This data transfer occurs all of the way along the shift register.
• Data from the output of the last flip-flop is lost.
• New data applied to the input of the first flip-flop is taken into the shift register.
Contents
To make a flip-flop toggle:-
-
S and
R are connected to 0
-
D is connected to
- The
D input is then always opposite to
Q- So toggling occurs on each successive clock pulse.
Contents
- D to
- All Resets joined together
- CK to previous Q for down counter and
for an up counter
- All resets joined together and connected to 0
- Only up-counters.
- AND gate output connected to reset.
- AND gate inputs connected to appropriate Q outputs.
- 5, Q0 & Q2
- 6, Q1 & Q2
- 10, Q1 & Q3
- 12, Q2 & Q3
Contents
Vout = A ×(V+ − V−)
Properties
• Differential amplifier
• Large input resistance ≈109Ω
• Large open-loop voltage gain, A, ≈106
• Low output resistance ≈100Ω
• Frequency compensated
• Gain-bandwidth product
Contents
• Input resistance = R1
• Output inverted
• Virtual earth point
• Saturation/clipping
• Bandwidth/voltage gain
• Minimum resistance 1kΩ
Contents
• Recognise by multiple inputs
• Input resistance of each input = R
• Behaves the same as the inverting amplifier
• Used in DAC & Mixer
Contents
• Very large input resistance ≈ 10
9Ω
• Beware input resistor to 0V
• Output in phase with input
• Voltage gain/bandwidth
• Minimum voltage gain = 1
• Voltage follower when R
f = 0 or R
1 = ∞
Contents
• low and unequal input resistance
• useful for reducing noise on differential signals
Contents
• Voltage gain ≈ 0.7 – 1
• Current gain ≈ 109
• Output voltage in phase with input
• Very large input resistance ≈ 109Ω
• Remember to subtract Vgs from Vin to obtain Vout
• N-channel and p-channel
Contents
• Provides power gain
• Needs op-amp to provide voltage gain
• Cross-over distortion at low volume
- Bias MOSFETs into conduction
• Saturation/clipping at high volume
- Increase supply voltage or reduce input voltage
Contents
• Negative feedback
Contents
• Heat sinks
- Metal
conduction
- Black
Radiation
- Large surface area
Convection
Radiation
- Fan
Convection
Contents
• Set in context
– read the context
– underline relevant details
• Look carefully at circuit diagrams
– circle and name sub-systems
• Focus on relevant bookwork descriptions and calculations
– answer these
• Attempt all sections
– no credit can be given if there is no attempt at an answer!
– only answer in the spaces provided
• Estimate, Calculate
– show your working
• State and explain
– do both!
Contents
